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ultralow distortion differential adc driver ADA4939-1/ada4939-2 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008 analog devices, inc. all rights reserved. features extremely low harmonic distortion ?102 dbc hd2 @ 10 mhz ?83 dbc hd2 @ 70 mhz ?77 dbc hd2 @ 100 mhz ?101 dbc hd3 @ 10 mhz ?97 dbc hd3 @ 70 mhz ?91 dbc hd3 @ 100 mhz low input voltage noise: 2.3 nv/hz high speed ?3 db bandwidth of 1.4 ghz, g = 2 slew rate: 6800 v/s, 25% to 75% fast overdrive recovery of <1 ns 0.5 mv typical offset voltage externally adjustable gain stable for differential gains 2 differential-to-differential or single-ended-to-differential operation adjustable output common-mode voltage single-supply operation: 3.3 v to 5 v applications adc drivers single-ended-to-differential converters if and baseband gain blocks differential buffers line drivers general description the ada4939 is a low noise, ultralow distortion, high speed differential amplifier. it is an ideal choice for driving high performance adcs with resolutions up to 16 bits from dc to 100 mhz. the output common-mode voltage is user adjustable by means of an internal common-mode feedback loop, allowing the ada4939 output to match the input of the adc. the internal feedback loop also provides exceptional output balance as well as suppression of even-order harmonic distortion products. with the ada4939, differential gain configurations are easily realized with a simple external feedback network of four resistors that determine the closed-loop gain of the amplifier. the ada4939 is fabricated using analog devices, inc., proprietary silicon-germanium (sige), complementary bipolar process, enabling it to achieve very low levels of distortion with an input voltage noise of only 2.3 nv/hz. the low dc offset and excellent dynamic performance of the ada4939 make it well suited for a wide variety of data acquisition and signal processing applications. functional block diagrams 1 ?fb 2 +in 3 ?in 4 +fb 11 ?out 12 pd 10 +out 9v ocm 5 + v s 6 + v s 7 + v s 8 + v s 1 5 ? v s 1 6 ? v s 1 4 ? v s 1 3 ? v s ADA4939-1 07429-001 figure 1. ADA4939-1 ada4939-2 1 ?in1 2 +fb1 3 +v s1 4 +v s1 5 ?fb2 6 +in2 15 ?v s2 16 ?v s2 17 v ocm1 18 +out1 14 pd2 13 ?out2 7 ? i n 2 8 + f b 2 9 + v s 2 1 1 v o c m 2 1 2 + o u t 2 1 0 + v s 2 2 1 ? v s 1 2 2 ? v s 1 2 3 ? f b 1 2 4 + i n 1 2 0 p d 1 1 9 ? o u t 1 07429-002 figure 2. ada4939-2 ? 60 ?110 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 1 10 100 harmonic distortion (dbc) frequency (mhz) hd2 hd3 v out, dm = 2v p-p 07429-021 figure 3. harmonic distortion vs. frequency the ada4939 is available in a pb-free, 3 mm 3 mm 16-lead lfcsp (ADA4939-1, single) or a pb-free, 4 mm 4 mm 24-lead lfcsp (ada4939-2, dual). the pinout has been optimized to facilitate pcb layout and minimize distortion. the ADA4939-1 and the ada4939-2 are specified to operate over the ?40c to +105c temperature range; both operate on supplies between 3.3 v and 5 v.
ADA4939-1/ada4939-2 rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagrams ............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 5 v operation ............................................................................... 3 3.3 v operation ............................................................................ 5 absolute maximum ratings ............................................................ 7 thermal resistance ...................................................................... 7 maximum power dissipation ..................................................... 7 esd caution .................................................................................. 7 pin configurations and function descriptions ........................... 8 typical performance characteristics ............................................. 9 test circ u its ..................................................................................... 15 operational description ................................................................ 16 definition of terms .................................................................... 16 theory of operation ...................................................................... 17 analyzing an application circuit ............................................ 17 setting the closed-loop gain .................................................. 17 stable for gains 2 ..................................................................... 17 estimating the output noise voltage ...................................... 17 impact of mismatches in the feedback networks ................. 18 calculating the input impedance for an application circuit ....................................................................................................... 19 input common-mode voltage range ..................................... 21 input and output capacitive ac-coupling ........................... 21 minimum r g value of 50 ...................................................... 21 setting the output common-mode voltage .......................... 21 layout, grounding, and bypassing .............................................. 22 high performance adc driving ................................................. 23 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 revision history 5/08revision 0: initial version
ADA4939-1/ada4939-2 rev. 0 | page 3 of 24 specifications 5 v operation t a = 25c, +v s = 5 v, ?v s = 0 v, v ocm = +v s /2, r f = 402 , r g = 200 , r t = 60.4 (when used), r l, dm = 1 k, unless otherwise noted. all specifications refer to single-ended input and differential outputs, unless otherwise noted. refer to figure 42 for signal definitions. d in to v out, dm performance tale parameter conditions min typ max unit dynamic performance ?3 db small signal bandwidth v out, dm = 0.1 v p-p 1400 mhz bandwidth for 0.1 db flatness v out, dm = 0.1 v p-p, ADA4939-1 300 mhz v out, dm = 0.1 v p-p, ada4939-2 90 mhz large signal bandwidth v out, dm = 2 v p-p 1400 mhz slew rate v out, dm = 2 v p-p, 25% to 75% 6800 v/s overdrive recovery time v in = 0 v to 1.5 v step, g = 3.16 <1 ns noise/harmonic performance see figure 41 for distortion test circuit second harmonic v out, dm = 2 v p-p, 10 mhz ?102 dbc v out, dm = 2 v p-p, 70 mhz ?83 dbc v out, dm = 2 v p-p, 100 mhz ?77 dbc third harmonic v out, dm = 2 v p-p, 10 mhz ?101 dbc v out, dm = 2 v p-p, 70 mhz ?97 dbc v out, dm = 2 v p-p, 100 mhz ?91 dbc imd f 1 = 70 mhz, f 2 = 70.1 mhz, v out, dm = 2 v p-p ?95 dbc f 1 = 140 mhz, f 2 = 140.1 mhz, v out, dm = 2 v p-p ?89 dbc voltage noise (rti) f = 100 khz 2.3 nv/hz input current noise f = 100 khz 6 pa/hz crosstalk f = 100 mhz, ada4939-2 ?80 db input characteristics offset voltage v os, dm = v out, dm /2, v din+ = v din? = 2.5 v ?3.4 0.5 +2.8 mv t min to t max variation 2.0 v/c input bias current ?26 ?10 +2.2 a t min to t max variation 0.5 a/c input offset current ?11.2 +0.5 +11.2 a input resistance differential 180 k common mode 450 k input capacitance 1 pf input common-mode voltage 1.1 3.9 v cmrr ?v out, dm /?v in, cm , ?v in, cm = 1 v ?83 ?77 db output characteristics output voltage swing maximum ?v out ; single-ended output, r f = r g = 10 k 0.9 4.1 v linear output current 100 ma output balance error ?v out, cm /?v out, dm , ?v out, dm = 1 v, 10 mhz, see figure 40 for test circuit ?64 db
ADA4939-1/ada4939-2 rev. 0 | page 4 of 24 v ocm to v out, cm performance table 2. parameter conditions min typ max unit v ocm dynamic performance ?3 db bandwidth 670 mhz slew rate v in = 1.5 v to 3.5 v, 25% to 75% 2500 v/s input voltage noise (rti) f = 100 khz 7.5 nv/hz v ocm input characteristics input voltage range 1.3 3.5 v input resistance 8.3 9.7 11.5 k input offset voltage v os, cm = v out, cm , v din+ = v din? = +v s /2 ?3.7 0.5 +3.7 mv v ocm cmrr v out, dm /v ocm , v ocm = 1 v ?90 ?73 db gain v out, cm /v ocm , v ocm = 1 v 0.97 0.98 0.99 v/v general performance table 3. parameter conditions min typ max unit power supply operating range 3.0 5.25 v quiescent current per amplifier 35.1 36.5 37.7 ma t min to t max variation 16 a/c powered down 0.26 0.32 0.38 ma power supply rejection ratio v out, dm /v s , v s = 1 v ?90 ?80 db power-down ( pd ) pd input voltage powered down 1 v enabled 2 v turn-off time 500 ns turn-on time 100 ns pd pin bias current per amplifier enabled pd = 5 v 30 a disabled pd = 0 v ?200 a operating temperature range ?40 +105 c
ADA4939-1/ada4939-2 rev. 0 | page 5 of 24 3.3 v operation t a = 25c, +v s = 3.3 v, ?v s = 0 v, v ocm = +v s /2, r f = 402 , r g = 200 , r t = 60.4 (when used), r l, dm = 1 k, unless otherwise noted. all specifications refer to single-ended input and differential outputs, unless otherwise noted. refer to figure 42 for signal definitions. d in to v out, dm performance tale parameter conditions min typ max unit dynamic performance ?3 db small signal bandwidth v out, dm = 0.1 v p-p 1400 mhz bandwidth for 0.1 db flatness v out, dm = 0.1 v p-p, ADA4939-1 300 mhz v out, dm = 0.1 v p-p, ada4939-2 90 mhz large signal bandwidth v out, dm = 2 v p-p 1400 mhz slew rate v out, dm = 2 v p-p, 25% to 75% 5000 v/s overdrive recovery time v in = 0 v to 1.0 v step, g = 3.16 <1 ns noise/harmonic performance see figure 41 for distortion test circuit second harmonic v out, dm = 2 v p-p, 10 mhz ?100 dbc v out, dm = 2 v p-p, 70 mhz ?90 dbc v out, dm = 2 v p-p, 100 mhz ?83 dbc third harmonic v out, dm = 2 v p-p, 10 mhz ?94 dbc v out, dm = 2 v p-p, 70 mhz ?82 dbc v out, dm = 2 v p-p, 100 mhz ?75 dbc imd f 1 = 70 mhz, f 2 = 70.1 mhz, v out, dm = 2 v p-p ?87 dbc f 1 = 140 mhz, f 2 = 140.1 mhz, v out, dm = 2 v p-p ?70 dbc voltage noise (rti) f = 100 khz 2.3 nv/hz input current noise f = 100 khz 6 pa/hz crosstalk f = 100 mhz, ada4939-2 ?80 db input characteristics offset voltage v os, dm = v out, dm /2, v din+ = v din? = +v s /2 ?3.5 0.5 +3.5 mv t min to t max variation 2.0 v/c input bias current ?26 ?10 +2.2 a t min to t max variation 0.5 a/c input offset current ?11.2 0.4 +11.2 input resistance differential 180 k common mode 450 k input capacitance 1 pf input common-mode voltage 0.9 2.4 v cmrr ?v out, dm /?v in, cm , ?v in, cm = 1 v ?85 ?75 db output characteristics output voltage swing maximum ?v out , single-ended output, r f = r g = 10 k 0.8 2.5 v linear output current 75 ma output balance error ?v out, cm /?v out, dm , ?v out, dm = 1 v, f = 10 mhz, see figure 40 for test circuit ?61 db
ADA4939-1/ada4939-2 rev. 0 | page 6 of 24 v ocm to v out, cm performance table 5. parameter conditions min typ max unit v ocm dynamic performance ?3 db bandwidth 560 mhz slew rate v in = 0.9 v to 2.4 v, 25% to 75% 1250 v/s input voltage noise (rti) f = 100 khz 7.5 nv/hz v ocm input characteristics input voltage range 1.3 1.9 v input resistance 8.3 9.7 11.2 k input offset voltage v os, cm = v out, cm , v din+ = v din? = 1.67 v ?3.7 0.5 +3.7 mv v ocm cmrr ?v out, dm /?v ocm , ?v ocm = 1 v ?75 ?73 db gain ?v out, cm /?v ocm , ?v ocm = 1 v 0.97 0.98 0.99 v/v general performance table 6. parameter conditions min typ max unit power supply operating range 3.0 5.25 v quiescent current per amplifier 32.8 34.5 36.0 ma t min to t max variation 16 a/c powered down 0.16 0.20 0.26 ma power supply rejection ratio ?v out, dm /?v s , ?v s = 1 v ?84 ?72 db power-down ( pd ) pd input voltage powered down 1 v enabled 2 v turn-off time 500 ns turn-on time 100 ns pd pin bias current per amplifier enabled pd = 3.3 v 26 a disabled pd = 0 v ?137 a operating temperature range ?40 +105 c
ADA4939-1/ada4939-2 rev. 0 | page 7 of 24 absolute maximum ratings table 7. parameter rating supply voltage 5.5 v power dissipation see figure 4 input current, +in, ?in, pd 5 ma storage temperature range ?65c to +125c operating temperature range ADA4939-1 ?40c to +105c ada4939-2 ?40c to +105c lead temperature (soldering, 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the device (including exposed pad) soldered to a high thermal conductivity 2s2p circuit board, as described in eia/jesd 51-7. table 8. thermal resistance package type ja unit ADA4939-1, 16-lead lfcsp (exposed pad) 98 c/w ada4939-2, 24-lead lfcsp (exposed pad) 67 c/w maximum power dissipation the maximum safe power dissipation in the ada4939 package is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150c, which is the glass transition temperature, the plastic changes its properties. even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ada4939. exceeding a junction temperature of 150c for an extended period can result in changes in the silicon devices, potentially causing failure. the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). the power dissipated due to the load drive depends upon the particular application. the power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. rms voltages and currents must be used in these calculations. airflow increases heat dissipation, effectively reducing ja . in addition, more metal directly in contact with the package leads/ exposed pad from metal traces, through holes, ground, and power planes reduces ja . figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the single 16-lead lfcsp (98c/w) and the dual 24-lead lfcsp (67c/w) on a jedec standard four-layer board with the exposed pad soldered to a pcb pad that is connected to a solid plane. 3.0 2.5 2.0 1.5 1.0 0.5 0 ?40 100 80 60 40 20 0 ?20 maximum power dissipation (w) ambient temperature (c) 07429-004 ADA4939-1 ada4939-2 figure 4. maximum power dissipation vs. ambient temperature for a four-layer board esd caution
ADA4939-1/ada4939-2 rev. 0 | page 8 of 24 pin configurations and function descriptions 1 ?fb 2 +in 3 ?in 4 +fb 11 ?out 12 pd 10 +out 9v ocm 5 + v s 6 + v s 7 + v s 8 + v s 1 5 ? v s 1 6 ? v s 1 4 ? v s 1 3 ? v s ADA4939-1 top view (not to scale) pin 1 indicator 07429-005 figure 5. ADA4939-1 pin configuration pin 1 indicator 1 2 3 4 5 6 15 16 17 18 14 13 7 8 9 1 1 1 2 1 0 2 1 2 2 2 3 2 4 + i n 1 2 0 1 9 top view (not to scale) ada4939-2 ?in1 + fb1 +v s1 +v s1 ? fb2 +in2 ?v s2 ?v s2 v ocm1 +out1 pd2 ?out2 ? i n 2 + f b 2 + v s 2 v o c m 2 + o u t 2 + v s 2 ? v s 1 ? v s 1 ? f b 1 p d 1 ? o u t 1 0 7429-006 figure 6. ada4939-2 pin configuration table 9. ADA4939-1 pin function descriptions pin no. mnemonic description 1 ?fb negative output for feedback component connection 2 +in positive input summing node 3 ?in negative input summing node 4 +fb positive output for feedback component connection 5 to 8 +v s positive supply voltage 9 v ocm output common-mode voltage 10 +out positive output for load connection 11 ?out negative output for load connection 12 pd power-down pin 13 to 16 ?v s negative supply voltage table 10. ada4939-2 pin function descriptions pin no. mnemonic description 1 ?in1 negative input summing node 1 2 +fb1 positive output feedback 1 3, 4 +v s1 positive supply voltage 1 5 ?fb2 negative output feedback 2 6 +in2 positive input summing node 2 7 ?in2 negative input summing node 2 8 +fb2 positive output feedback 2 9, 10 +v s2 positive supply voltage 2 11 v ocm2 output common-mode voltage 2 12 +out2 positive output 2 13 ?out2 negative output 2 14 pd2 power-down pin 2 15, 16 ?v s2 negative supply voltage 2 17 v ocm1 output common-mode voltage 1 18 +out1 positive output 1 19 ?out1 negative output 1 20 pd1 power-down pin 1 21, 22 ?v s1 negative supply voltage 1 23 ?fb1 negative output feedback 1 24 +in1 positive input summing node 1
ADA4939-1/ada4939-2 rev. 0 | page 9 of 24 typical performance characteristics t a = 25c, +v s = 5 v, ?v s = 0 v, v ocm = +v s /2, r g = 200 , r f = 402 , r t = 60.4 , g = 1, r l, dm = 1 k, unless otherwise noted. refer to figure 39 for test setup. refer to figure 42 for signal definitions. 2 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 1 10 100 1k normalized closed-loop gain (db) frequency (mhz) g = +2.00 g = +3.16 g = +5.00 r g = 200 ? , r t = 60.4 ? r g = 127 ? , r t = 66.3 ? r g = 80.6 ? , r t = 76.8 ? v out, dm = 100mv p-p 07429-007 figure 7. small signal frequency response for various gains 3 ?12 ?10 ?8 ?6 ?4 ?2 0 2 ?11 ?9 ?7 ?5 ?3 ?1 1 1 10 100 1k normalized closed-loop gain (db) frequency (mhz) v s = 3.3v v s = 5.0v 07429-008 v out, dm = 100mv p-p figure 8. small signal frequency response for various supplies 3 ?12 ?10 ?8 ?6 ?4 ?2 0 2 ?11 ?9 ?7 ?5 ?3 ?1 1 1 10 100 1k normalized closed-loop gain (db) frequency (mhz) ?40c +25c +105c 07429-009 v out, dm = 100mv p-p figure 9. small signal frequency response for various temperatures 2 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 1 10 100 1k normalized closed-loop gain (db) frequency (mhz) g = +2.00 g = +3.16 g = +5.00 07429-010 r g = 200 ? , r t = 60.4 ? r g = 127 ? , r t = 66.3 ? r g = 80.6 ? , r t = 76.8 ? v out, dm = 2v p-p figure 10. large signal frequency response for various gains 2 ?12 ?10 ?8 ?6 ?4 ?2 0 1 10 100 1k normalized closed-loop gain (db) frequency (mhz) v s = 3.3v v s = 5.0v 07429-011 v out, dm = 2v p-p figure 11. large signal frequenc y response for various supplies 3 ?12 ?10 ?8 ?6 ?4 ?2 0 2 ?11 ?9 ?7 ?5 ?3 ?1 1 1 10 100 1k normalized closed-loop gain (db) frequency (mhz) ?40c +25c +105c 07429-012 v out, dm = 2v p-p figure 12. large signal frequency response for various temperatures
ADA4939-1/ada4939-2 rev. 0 | page 10 of 24 3 ?12 ?10 ?8 ?6 ?4 ?2 0 2 ?11 ?9 ?7 ?5 ?3 ?1 1 1 10 100 1k normalized closed-loop gain (db) frequency (mhz) r l = 1k ? r l = 200 ? 07429-013 v out, dm = 100mv p-p figure 13. small signal frequency response for various loads 6 ?9 ?6 ?3 3 0 1 10 100 1k v ocm gain (db) frequency (mhz) v ocm = 1.0v v ocm = 3.9v v ocm = 2.5v 07429-019 v out, dm = 100mv p-p figure 14. v ocm small signal frequency response at various dc levels 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 1 10 100 1k normalized closed-loop gain (db) frequency (mhz) r l = 1k ? r l = 200 ? r l = 1k ? out1 r l = 1k ? out2 r l = 200 ? out1 r l = 200 ? out2 07429-020 v out, dm = 100mv p-p figure 15. 0.1 db flatness small signal response for various loads 3 ?12 ?10 ?8 ?6 ?4 ?2 0 2 ?11 ?9 ?7 ?5 ?3 ?1 1 1 10 100 1k normalized closed-loop gain (db) frequency (mhz) r l = 1k ? r l = 200 ? 07429-016 v out, dm = 2v p-p figure 16. large signal frequency response for various loads ?55 ?115 ?110 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 1 10 100 harmonic distortion (dbc) frequency (mhz) v out, dm = 2v p-p hd2, g = 2 hd3, g = 2 hd2, g = 3.16 hd3, g = 3.16 hd2, g = 5 hd3, g = 5 07429-022 figure 17. harmonic distortion vs. frequency at various gains ? 60 ?110 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 1 10 100 harmonic distortion (dbc) frequency (mhz) hd2, r l, dm = 1k ? hd3, r l, dm = 1k ? hd2, r l, dm = 200 ? hd3, r l, dm = 200 ? v out, dm = 2v p-p v s = 2.5v 07429-023 figure 18. harmonic distortion vs. frequency at various loads
ADA4939-1/ada4939-2 rev. 0 | page 11 of 24 ? 60 ?110 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 1 10 100 harmonic distortion (dbc) frequency (mhz) hd2, v s (split supply) = 2.5v hd3, v s (split supply) = 2.5v hd2, v s (split supply) = 1.65v hd3, v s (split supply) = 1.65v v out, dm = 2v p-p 07429-062 figure 19. harmonic distortion vs. frequency at various supplies ? 40 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 1.0 4.0 3.8 3.63.43.23.02.82.62.4 2.2 2.01.81.61.41.2 distortion (dbc) v ocm (v) hd2, f = 10mhz hd3, f = 10mhz hd2, f = 70mhz hd3, f = 70mhz v out, dm = 2v p-p 07429-025 figure 20. harmonic distortion vs. v ocm at various frequencies ? 40 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 1 . 21 . 41 . 61 . 82 distortion (dbc) v ocm (v) . 0 hd2, f = 10mhz hd3, f = 10mhz hd2, f = 70mhz hd3, f = 70mhz v out, dm = 2v p-p 07429-026 figure 21. harmonic distortion vs. v ocm at various frequencies ? 40 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 07 654321 distortion (dbc) v out, dm (v p-p) hd2, v s = 5.0 hd3, v s = 5.0 hd2, v s = 3.3 hd3, v s = 3.3 07429-024 figure 22. harmonic distortion vs. v out, dm and supply voltage, f = 10 mhz 10 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 69.5 70.5 70.470.3 70.270.170.069.969.869.7 69.6 normalized spectrum (dbc) frequency (mhz) v out, dm = 2v p-p v s = 2.5v 07429-028 figure 23. 70 mhz intermodulation distortion ? 30 ?35 ?40 ?45 ?50 ?55 ?60 ?65 ?70 11 0 100 cmrr (db) frequency (mhz) 1 k r l, dm = 200 ? 07429-029 figure 24. cmrr vs. frequency
ADA4939-1/ada4939-2 rev. 0 | page 12 of 24 ? 60 ?120 ?110 ?100 ?90 ?80 ?70 1 10 100 harmonic distortion (dbc) frequency (mhz) v out, dm =hd2, = 1v p-p v out, dm =hd3, = 1v p-p v out, dm =hd2, = 2v p-p v out, dm =hd3, = 2v p-p 07429-027 v s = 1.65v figure 25. harmonic distortion vs. frequency at various output voltages ? 30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 11 0 100 psrr (db) frequency (mhz) 1 k r l, dm = 200 ? 07429-031 figure 26. psrr vs. frequency, r l = 200 0 ?5 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 1 10 100 1k s-parameters (db) frequency (mhz) r l, dm = 200 ? s11 s22 07429-032 figure 27. return loss (s11, s22) vs. frequency ? 30 ?35 ?40 ?45 ?50 ?55 ?60 ?65 ?70 11 0 100 output balance (db) frequency (mhz) 1 k r l, dm = 200 ? 07429-030 figure 28. output balance vs. frequency 70 ?10 100 ?350 ?300 ?250 ?200 ?150 ?100 ?50 0 50 0 10 20 30 40 50 60 0.01 10k 1k 100 10 1 0.1 gain (db) phase (degrees) frequency (mhz) gain phase 07429-034 figure 29. open-loop gain and phase vs. frequency 8 ?8 ?6 ?4 ?2 0 2 4 6 06 50 40 30 20 10 voltage (v) time (ns) 0 v in 3.16v v out 07429-035 figure 30. overdrive recovery, g = 3.16
ADA4939-1/ada4939-2 rev. 0 | page 13 of 24 ? 60 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 1 10 100 spurious-free dynamic range (dbc) frequency (mhz) v out, dm = 2v p-p v s = 2.5v r l = 1k ? r l = 200 ? 07429-033 figure 31. spurious-free dynamic range vs. frequency at various loads 0.12 0.10 0.08 0.06 0.04 0.02 0 ?0.02 01 0 987654321 output voltage (v) time (ns) 07429-038 figure 32. small signal pulse response 2.60 2.40 2.45 2.50 2.55 02 0 18161412 10 8642 output common-mode voltage (v) time (ns) 07429-039 figure 33. v ocm small signal pulse response ? 40 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 11 100 10 crosstalk (db) frequency (mhz) k r l, dm = 200 ? input amp 1 to output amp 2 input amp 2 to output amp 1 07429-044 figure 34. crosstalk vs. frequency for ada4939-2 4 ?4 ?3 ?2 ?1 0 1 2 3 01 0 987654321 output voltage (v) time (ns) 07429-041 figure 35. large signal pulse response 4.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 02 0 18161412 10 8642 output common-mode voltage (v) time (ns) 07429-042 figure 36. v ocm large signal pulse response
ADA4939-1/ada4939-2 rev. 0 | page 14 of 24 3.5 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 0 1000900800700600500400300200100 voltage (v) time (ns) v out, dm r l, dm = 200 ? pd 07429-043 1k 1 10 100 10 10m 1m 100k 10k 1k 100 input voltage noise (nv/ hz) frequency (hz) 07429-045 figure 37. pd response time figure 38. voltage noise spectral density, rti
ADA4939-1/ada4939-2 rev. 0 | page 15 of 24 test circuits ada4939 1k? 5v 402 ? 200 ? 50? 200 ? 0.1f 0.1f 402 ? v ocm 60.4 ? v in 07429-046 figure 39. equivalent basic test circuit, g = 2 ada4939 +2.5v 0.1f ?2.5v 402 ? 200 ? 50 ? 200 ? 49.9 ? 49.9 ? network analyzer input ac-coupled network analyzer output ac-coupled 50? 402 ? 49.9 ? 49.9 ? v ocm 60.4 ? 60.4 ? v in 07429-047 figure 40. test circuit for output balance, cmrr ada4939 5v 402 ? 200 ? 50? 200 ? 442 ? 442 ? 0.1f 0.1f 402 ? v ocm 60.4 ? 261 ? 200 ? 2:1 50 ? ct v in low-pass filter 0.1f 0.1f dual filter 07429-048 figure 41. test circuit for distortion measurements
ADA4939-1/ada4939-2 rev. 0 | page 16 of 24 operational description definition of terms +in ?in +out ?out +d in ? fb +fb ?d in v ocm r g r f r g v out, dm r l, dm r f ada4939 07429-049 figure 42. circuit definitions differential voltage differential oltage refer to te difference eteen to node oltage or eample, te output differential oltage or euialentl, output differential-mode oltage i defined a v out, dm v +out ? v ?out ere v +out and v ?out reer to te voltaes at te +out and ?out terminals it respect to a common reerence common-mode voltage common-mode oltage refer to te aerage of to node oltage te output common-mode oltage i defined a v out, cm v +out + v ?out 2 balance output alance i a meaure of o cloe te differential ignal are to eing eual in amplitude and oppoite in pae output alance i mot eail determined placing a ell-matced reitor diider eteen te differential oltage node and comparing te magnitude of te ignal at te diider midpoint it te magnitude of te differential ignal ee igure b ti definition, output alance i te magnitude of te output common-mode oltage diided te magnitude of te output differential mode oltage dmout cmout v v error balance output , , =
ADA4939-1/ada4939-2 rev. 0 | page 17 of 24 theory of operation the ada4939 differs from conventional op amps in that it has two outputs whose voltages move in opposite directions and an additional input, v ocm . like an op amp, it relies on high open- loop gain and negative feedback to force these outputs to the desired voltages. the ada4939 behaves much like a standard voltage feedback op amp and facilitates single-ended-to-differential conversions, common-mode level shifting, and amplifications of differential signals. like an op amp, the ada4939 has high input impedance and low output impedance. because it uses voltage feedback, the ada4939 manifests a nominally constant gain- bandwidth product. two feedback loops are employed to control the differential and common-mode output voltages. the differential feedback, set with external resistors, controls only the differential output voltage. the common-mode feedback controls only the common-mode output voltage. this architecture makes it easy to set the output common-mode level to any arbitrary value within the specified limits. the output common-mode voltage is forced, by the internal common-mode feedback loop, to be equal to the voltage applied to the v ocm input. the internal common-mode feedback loop produces outputs that are highly balanced over a wide frequency range without requiring tightly matched external components. this results in differential outputs that are very close to the ideal of being identical in amplitude and are exactly 180 apart in phase. analyzing an application circuit the ada4939 uses high open-loop gain and negative feedback to force its differential and common-mode output voltages in such a way as to minimize the differential and common-mode error voltages. the differential error voltage is defined as the voltage between the differential inputs labeled +in and ?in (see figure 42 ). for most purposes, this voltage can be assumed to be zero. similarly, the difference between the actual output common-mode voltage and the voltage applied to v ocm can also be assumed to be zero. starting from these two assumptions, any application circuit can be analyzed. setting the closed-loop gain the differential-mode gain of the circuit in figure 42 can be determined by g f dmin dmout r r v v = , , this presumes that the input resistors (r g ) and feedback resistors (r f ) on each side are equal. stable for gains 2 the ada4939 frequency response exhibits excessive peaking for differential gains <2; therefore, the part should be operated with differential gains 2. estimating the output noise voltage the differential output noise of the ada4939 can be estimated using the noise model in figure 43 . the input-referred noise voltage density, v nin , is modeled as a differential input, and the noise currents, i nin? and i nin+ , appear between each input and ground. the output voltage due to v nin is obtained by multiplying v nin by the noise gain, g n (defined in the g n equation that follows). the noise currents are uncorrelated with the same mean-square value, and each produces an output voltage that is equal to the noise current multiplied by the associated feedback resistance. the noise voltage density at the v ocm pin is v ncm . when the feedback networks have the same feedback factor, as in most cases, the output noise due to v ncm is common-mode. each of the four resistors contributes (4ktr xx ) 1/2 . the noise from the feedback resistors appears directly at the output, and the noise from the gain resistors appears at the output multiplied by r f /r g . table 11 summarizes the input noise sources, the multiplication factors, and the output-referred noise density terms. ada4939 + r f2 v nod v ncm v ocm v nin r f1 r g2 r g1 v nrf1 v nrf2 v nrg1 v nrg2 i nin+ i nin? 07429-050 figure 43. noise model
ADA4939-1/ada4939-2 rev. 0 | page 18 of 24 table 11. output noise voltag e density calculations for matched feedback networks input noise contribution input noise term input noise voltage density output multiplication factor differential output noise voltage density term differential input v nin v nin g n v no1 = g n (v nin ) inverting input i nin i nin (r f2 ) 1 v no2 = (i nin )(r f2 ) noninverting input i nin i nin (r f1 ) 1 v no3 = (i nin )(r f1 ) v ocm input v ncm v ncm 0 v no4 = 0 gain resistor r g1 v nrg1 (4ktr g1 ) 1/2 r f1 /r g1 v no5 = (r f1 /r g1 )(4ktr g1 ) 1/2 gain resistor r g2 v nrg2 (4ktr g2 ) 1/2 r f2 /r g2 v no6 = (r f2 /r g2 )(4ktr g2 ) 1/2 feedback resistor r f1 v nrf1 (4ktr f1 ) 1/2 1 v no7 = (4ktr f1 ) 1/2 feedback resistor r f2 v nrf2 (4ktr f2 ) 1/2 1 v no8 = (4ktr f2 ) 1/2 table 12. differential input, dc-coupled nominal gain (db) r f () r g () r in, dm () differential output noise density (nv/hz) 6 402 200 400 9.7 10 402 127 254 12.4 14 402 80.6 161 16.6 table 13. single-ended ground-referenced input, dc-coupled, r s = 50 nominal gain (db) r f () r g1 () r t () r in, cm () r g2 () 1 differential output noise density (nv/hz) 6 402 200 60.4 301 228 9.1 10 402 127 66.5 205 155 11.1 14 402 80.6 76.8 138 111 13.5 1 r g2 = r g1 + (r s ||r t ). similar to the case of a conventional op amp, the output noise voltage densities can be estimated by multiplying the input- referred terms at +in and ?in by the appropriate output factor, where ( ) 21 n | g + = g1 f1 g1 1 rr r + = g2 f2 g2 2 rr r + = g f n r r g +== = = 2 noi nod vv tale 12 and tale 1 list several common ain settins, associated resistor values, input impedance, and output noise densit or ot alanced and unalanced input coniurations impact of mismatches in the feedback networks as previously mentioned, even if the external feedback networks (r f /r g ) are mismatched, the internal common-mode feedback loop still forces the outputs to remain balanced. the amplitudes of the signals at each output remain eual and 180 out of phase. the input-to-output differential mode gain varies proportionately to the feedback mismatch, but the output balance is unaffected. the gain from the v ocm pin to v o, dm is eual to 2(1 ? 2)/(1 2) when 1 = 2, this term goes to zero and there is no differential output voltage due to the voltage on the v ocm input (including noise). the extreme case occurs when one loop is open and the other has 100% feedback in this case, the gain from v ocm input to v o, dm is either 2 or ?2, depending on which loop is closed. the feedback loops are nominally matched to within 1% in most applications, and the output noise and offsets due to the v ocm input are negligible. if the loops are intentionally mismatched by a large amount, it is necessary to include the gain term from v ocm to v o, dm and account for the extra noise. for example, if 1 = 0.5 and 2 = 0.25, the gain from v ocm to v o, dm is 0.67. if the v ocm pin is set to 2.5 v, a differential offset voltage is present at the output of (2.5 v)(0.67) = 1.67 v. the differential output noise contribution is (7.5 nv/hz)(0.67) = 5 nv/hz. both of these results are undesirable in most applications therefore, it is best to use nominally matched feedback factors.
ADA4939-1/ada4939-2 rev. 0 | page 19 of 24 mismatched feedback networks also result in a degradation of the ability of the circuit to reject input common-mode signals, much the same as for a four-resistor difference amplifier made from a conventional op amp. as a practical summarization of the above issues, resistors of 1% tolerance produce a worst-case input cmrr of approximately 40 db, a worst-case differential-mode output offset of 25 mv due to a 2.5 v v ocm input, negligible v ocm noise contribution, and no significant degradation in output balance error. calculating the input impedance for an application circuit the effective input impedance of a circuit depends on whether the amplifier is being driven by a single-ended or differential signal source. for balanced differential input signals, as shown in figure 44 , the input impedance (r in, dm ) between the inputs (+d in and ?d in ) is simply r in, dm = 2 r g . +v s ada4939 +in ?in r f r f +d in ?d in v ocm r g r g v out, dm 07429-051 figure 44. ada4939 configured for balanced (differential) inputs for an unbalanced, single-ended input signal (see figure 45 ), the input impedance is () ? ? ? ? ? ? ? ? ? ? ? ? + ? = 2 1 , ada4939 r l v out, dm +v s ?v s r g r g r f r f v ocm r in , se 07429-052 figure 45. ada4939 with unba lanced (single-ended) input the input impedance of the circuit is effectively higher than it would be for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage across the input resistor r g . the common-mode voltage at the amplifier input terminals can be easily determined by noting that the voltage at the inverting input is equal to the noninverting output voltage divided down by the voltage divider formed by r f and r g in the lower loop. this voltage is present at both input terminals due to negative voltage feedback and is in phase with the input signal, thus reducing the effective voltage across r g in the upper loop and partially bootstrapping r g . terminating a sing le-ended input this section deals with how to properly terminate a single- ended input to the ada4939 with a gain of 2, r f = 400 , and r g = 200 . an example using an input source with a terminated output voltage of 1 v p-p and source resistance of 50 illustrates the four simple steps that must be followed. note that because the terminated output voltage of the source is 1 v p-p, the open circuit output voltage of the source is 2 v p-p. the source shown in figure 46 indicates this open-circuit voltage. 1. the input impedance must be calculated using the formula 300 )400200(2 400 1 200 )(2 1 = ? ? ? ? ? ? ? ? ? ? ? ? + ? = ? ? ? ? ? ? ? ? ? ? ? ? + ? = r s 50 ? v s 2v p-p r in 300 ? ada4939 r l v out, dm +v s ?v s r g 200 ? r g 200 ? r f 400 ? r f 400 ? v ocm 07429-053 figure 46. calculating sing le-ended input impedance r in
ADA4939-1/ada4939-2 rev. 0 | page 20 of 24 2. in order to match the 50 source resistance, the termi- nation resistor, r t , is calculated using r t ||300 = 50 . the closest standard 1% value for r t is 60.4 . ada4939 r l v out, dm +v s ?v s r s 50 ? r g 200? r g 200? r f 400? r f 400 ? v ocm v s 2v p-p r in 50? r t 60.4 ? 07429-054 figure 47. adding termination resistor r t 3. it can be seen from figure 47 that the effective r g in the upper feedback loop is now greater than the r g in the lower loop due to the addition of the termination resistors. to compensate for the imbalance of the gain resistors, a correction resistor (r ts ) is added in series with r g in the lower loop. r ts is equal to the thevenin equivalent of the source resistance r s and the termination resistance r t and is equal to r s ||r t . r s 50 ? v s 2 v p- p r t 60.4 ? r th 27.4 ? v th 1.09v p-p 0 7429-055 figure 48. calculating the thevenin equivalent r ts = r th = r s ||r t = 27.4 . note that v th is greater than 1 v p-p, which was obtained with r t = 50 . the modified circuit with the thevenin equivalent of the terminated source and r ts in the lower feedback loop is shown in figure 49 . ada4939 r l v out, dm +v s ?v s r th 27.4 ? r g 200? r g 200? r f 400? r f 400? v ocm v th 1.09v p-p r ts 27.4 ? 07429-056 figure 49. thevenin equivalent and matched gain resistors figure 49 presents a tractable circuit with matched feedback loops that can be easily evaluated. it is useful to point out two effects that occur with a terminated input. the first is that the value of r g is increased in both loops, lowering the overall closed-loop gain. the second is that v th is a little larger than 1 v p-p, as it would be if r t = 50 . these two effects have opposite impacts on the output voltage, and for large resistor values in the feedback loops (~1 k), the effects essentially cancel each other out. for small r f and r g , however, the diminished closed-loop gain is not canceled completely by the increased v th . this can be seen by evaluating figure 49 . the desired differential output in this example is 2 v p-p because the terminated input signal was 1 v p-p and the closed-loop gain = 2. the actual differential output voltage, however, is equal to (1.09 v p-p)(400/227.4) = 1.92 v p-p. to obtain the desired output voltage of 2 v p-p, a final gain adjustment can be made by increasing r f without modifying any of the input circuitry. this is discussed in step 4. 4. the feedback resistor value is modified as a final gain adjustment to obtain the desired output voltage. to make the output voltage v out = 2 v p-p, r f must be calculated using the following formula: : : 417 09.1 4.2272 , pp pp th ts g dm out f v v v rrvdesired r the closest standard 1 % values to 417 are 412 and 422 . choosing 422 gives a differential output voltage of 2.02 v p-p. the final circuit is shown in figure 50 . ada4939 r l v out, dm 2.02v p-p +v s ?v s r s 50? r g 200 ? r g 200 ? r f 422 ? r f 422 ? v ocm v s 2v p-p 1v p-p r t 60.4 ? r ts 27.4 ? 07429-057 figure 50. terminated single-ende d-to-differential system with g = 2
ADA4939-1/ada4939-2 rev. 0 | page 21 of 24 input common-mode voltage range the ada4939 input common-mode range is centered between the two supply rails, in contrast to other adc drivers with level-shifted input ranges, such as the ada4937 . the centered input common- mode range is best suited to ac-coupled, differential-to-differential and dual supply applications. for 5 v single-supply operation, the input common-mode range at the summing nodes of the amplifier is specified as 1.1 v to 3.9 v and is specified as 0.9 v to 2.4 v with a 3.3 v supply. to avoid nonlinearities, the voltage swing at the +in and ?in terminals must be confined to these ranges. input and output capacitive ac coupling input ac coupling capacitors can be inserted between the source and r g . this ac coupling blocks the flow of the dc common- mode feedback current and causes the ada4939 dc input common-mode voltage to equal the dc output common-mode voltage. these ac coupling capacitors must be placed in both loops to keep the feedback factors matched. output ac coupling capacitors can be placed in series between each output and its respective load. see figure 54 for an example that uses input and output capacitive ac coupling. minimum r g value of 50 due to the wide bandwidth of the ada4939, the value of r g must be greater than or equal to 50 to provide sufficient damping in the amplifier front end. in the terminated case, r g includes the thevenin resistance of the source and load terminations. setting the output common-mode voltage the v ocm pin of the ada4939 is internally biased with a voltage divider comprising two 20 k resistors at a voltage approximately equal to the midsupply point, [(+v s ) + (?v s )]/2. because of this internal divider, the v ocm pin sources and sinks current, depending on the externally applied voltage and its associated source resistance. relying on the internal bias results in an output common-mode voltage that is within about 100 mv of the expected value. in cases where more accurate control of the output common- mode level is required, it is recommended that an external source or resistor divider be used with source resistance less than 100 . the output common-mode offset listed in the specifications section assumes that the v ocm input is driven by a low impedance voltage source. it is also possible to connect the v ocm input to a common-mode level (cml) output of an adc. however, care must be taken to ensure that the output has sufficient drive capability. the input impedance of the v ocm pin is approximately 10 k. if multiple ada4939 devices share one reference output, it is recommended that a buffer be used.
ADA4939-1/ada4939-2 rev. 0 | page 22 of 24 layout, grounding, and bypassing as a high speed device, the ada4939 is sensitive to the pcb environment in which it operates. realizing its superior performance requires attention to the details of high speed pcb design. this section shows a detailed example of how the ADA4939-1 was addressed. the first requirement is a solid ground plane that covers as much of the board area around the ADA4939-1 as possible. however, the area near the feedback resistors (r f ), gain resistors (r g ), and the input summing nodes (pin 2 and pin 3) should be cleared of all ground and power planes (see figure 51 ). clearing the ground and power planes minimizes any stray capacitance at these nodes and prevents peaking of the response of the amplifier at high frequencies. the thermal resistance, ja , is specified for the device, including the exposed pad, soldered to a high thermal conductivity four-layer circuit board, as described in eia/jesd 51-7. 0 7429-058 figure 51. ground and power plane voiding in vicinity of r f and r g the power supply pins should be bypassed as close to the device as possible and directly to a nearby ground plane. high frequency ceramic chip capacitors should be used. it is recommended that two parallel bypass capacitors (1000 pf and 0.1 f) be used for each supply. the 1000 pf capacitor should be placed closer to the device. further away, low frequency bypassing should be provided, using 10 f tantalum capacitors from each supply to ground. signal routing should be short and direct to avoid parasitic effects. wherever complementary signals exist, a symmetrical layout should be provided to maximize balanced performance. when routing differential signals over a long distance, pcb traces should be close together, and any differential wiring should be twisted such that loop area is minimized. doing this reduces radiated energy and makes the circuit less susceptible to interference. 1.30 0.80 0.80 1.30 07429-059 figure 52. recommended pcb thermal attach pad dimensions (millimeters) 0.30 plated via hole 1.30 ground plane power plane bottom metal top metal 07429-060 figure 53. cross-section of four-layer pcb showing thermal via connection to buried ground plane (dimensions in millimeters)
ADA4939-1/ada4939-2 rev. 0 | page 23 of 24 high performance adc driving the ada4939 is ideally suited for broadband ac-coupled and differential-to-differential applications on a single supply. the circuit in figure 54 shows a front-end connection for an ada4939 driving an ad9445 , 14-bit, 105 msps adc, with ac coupling on the ada4939 input and output. (the ad9445 achieves its optimum performance when driven differentially.) the ada4939 eliminates the need for a transformer to drive the adc and performs a single-ended-to-differential conversion and buffering of the driving signal. the ada4939 is configured with a single 5 v supply and gain of 2 for a single-ended input to differential output. the 60.4 termination resistor, in parallel with the single-ended input impedance of approximately 300 , provides a 50 termination for the source. the additional 27.4 (227.4 total) at the inverting input balances the parallel impedance of the 50 source and the termination resistor driving the noninverting input. in this example, the signal generator has a 1 v p-p symmetric, ground-referenced bipolar output when terminated in 50 . the v ocm pin of the ada4939 is bypassed for noise reduction and left floating such that the internal divider sets the output common-mode voltage nominally at midsupply. because the inputs are ac-coupled, no dc common-mode current flows in the feedback loops, and a nominal dc level of midsupply is present at the amplifier input terminals. besides placing the amplifier inputs at their optimum levels, the ac coupling technique lightens the load on the amplifier and dissipates less power than applications with dc-coupled inputs. with an output common- mode voltage of nominally 2.5 v, each ada4937 output swings between 2.0 v and 3.0 v, providing a gain of 2 and a 2 v p-p differential signal to the adc input. the output of the amplifier is ac-coupled to the adc through a second-order, low-pass filter with a cutoff frequency of 100 mhz. this reduces the noise bandwidth of the amplifier and isolates the driver outputs from the adc inputs. the ad9445 is configured for a 2 v p-p full-scale input by connecting the sense pin to agnd, as shown in figure 54 . 07429-061 vin? vin+ 47pf 30nh 30nh 24.3 ? 24.3 ? 50? signal generator 200 ? 200 ? v ocm 5v ada4939 + 60.4 ? 412? 27.4 ? 412 ? 14 buffer t/h adc clock/ timing ref sense agnd 0.1f 0.1f 0.1f 0.1f 0.1f ad9445 3.3v (a) avdd1 5v (a) avdd2 3.3v (d) drvdd figure 54. ada4939 driving an ad9445 ad c with ac-coupled input and output
ADA4939-1/ada4939-2 rev. 0 | page 24 of 24 outline dimensions 1 0.50 bsc 0.60 max pin 1 indicator 1.50 ref 0.50 0.40 0.30 0.25 min 0.45 2.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicato r 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 3.00 bsc sq * 1.45 1.30 sq 1.15 exposed pad 16 5 13 8 9 12 4 (bottom view) * compliant to jedec standards mo-220-veed-2 except for exposed pad dimension. figure 55. 16-lead lead frame chip scale package [lfcsp_vq] 3 mm 3 mm body, very thin quad (cp-16-2) dimensions shown in millimeters 1 24 6 7 13 19 18 12 2.25 2.10 sq 1.95 0.60 max 0.50 0.40 0.30 0.30 0.23 0.18 2.50 ref 0.50 bsc 12 max 0.80 max 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indicator top view 3.75 bsc sq 4.00 bsc sq pin 1 indicator 0.60 max coplanarity 0.08 0.20 ref 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vggd-2 figure 56. 24-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-24-1) dimensions shown in millimeters ordering guide model temperature range package description pa ckage option ordering quantity branding ADA4939-1ycpz-r2 1 ?40c to +105c 16-lead lfcsp_vq cp-16-2 250 h1e ADA4939-1ycpz-rl 1 ?40c to +105c 16-lead lfcsp_vq cp-16-2 5,000 h1e ADA4939-1ycpz-r7 1 ?40c to +105c 16-lead lfcsp_vq cp-16-2 1,500 h1e ada4939-2ycpz-r2 1 ?40c to +105c 24-lead lfcsp_vq cp-24-1 250 ada4939-2ycpz-rl 1 ?40c to +105c 24-lead lfcsp_vq cp-24-1 5,000 ada4939-2ycpz-r7 1 ?40c to +105c 24-lead lfcsp_vq cp-24-1 1,500 1 z = rohs compliant part. ?2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07429-0-5/08(0)

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